Optoelectronic package and method for making same

ABSTRACT

An optoelectronic package includes a substrate and a cover element bonded onto the substrate. The cover element defines a cavity for accommodating semiconductor chips and optoelectronic components. The cover element includes a first adhesive bonding area configured for receiving a first adhesive and being bonded with a predetermined region of the substrate by the first adhesive. The engagement of the cover element and the substrate defines a second adhesive bonding area. The second adhesive bonding area is configured for receiving a second adhesive and confining the second adhesive within a localized area. A method for making an optoelectronic package is also provided.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional application of U.S. patent applicationSer. No. 13/860,531 filed on Apr. 11, 2013 which claims the benefit ofU.S. Provisional Patent Application No. 61/623,078 filed on Apr. 12,2012, the contents of which is hereby incorporated by reference.

FIELD OF THE PATENT APPLICATION

The present patent application generally relates to semiconductor chippackaging technologies and more specifically to an optoelectronicpackage that maintains high alignment precision and high bondingstrength, and a method for making the same.

BACKGROUND

Semiconductor electronics components packaged using chip-on-board (COB)processes often employ a cover element to protect silicon chips fromphysical damages as well as particle and moisture attacks. This coverelement is often bonded onto a circuit substrate using adhesives. Theunderside of the cover element forms a protective cavity in which thesilicon chips are located. To ensure reliability of the package, astrong bonding force between the cover element and the substrate isrequired throughout the lifetime of the product.

As illustrated in FIG. 1, when such packaging is used foroptoelectronics components, the cover element may also serve additionaloptical functions. For example, lens structures may be formed on thecover element to facilitate optical signal coupling. This additionaloptical functionality can only be realized if the alignment of the coverelement to the optoelectronics chips inside the cavity is preciselymaintained (<15 um misalignment) during the assembly process andthroughout the lifetime of the product.

Two types of adhesives are conventionally used in bonding the coverelement to the substrate: UV-activated epoxy and thermally-activatedepoxy. The former provides fast curing time and minimal curing shiftwhile the latter provides stronger bonding strength but requires longercuring time and introduces larger post-curing shift between the twoparts.

SUMMARY

The present patent application is directed to an optoelectronic package.In one aspect, the optoelectronic package includes a substrate and acover element bonded onto the substrate. The cover element defines acavity for accommodating semiconductor chips and optoelectroniccomponents. The cover element includes a first adhesive bonding areaconfigured for receiving a first adhesive and being bonded with apredetermined region of the substrate by the first adhesive. Theengagement of the cover element and the substrate defines a secondadhesive bonding area. The second adhesive bonding area is configuredfor receiving a second adhesive and confining the second adhesive withina localized area.

The cover element may include two steps defining two cutout regionsformed at two opposite sides of the cover element respectively, theengagement of the two steps and the substrate defining the secondadhesive bonding area.

The cover element may include two thinned-down regions formed at twoopposite sides of the cover element respectively, the engagement of thetwo thinned-down regions and the substrate defining the second adhesivebonding area. A through hole may be formed within each of thethinned-down regions and configured for improving the confinement of thesecond adhesive.

Two through slots may be formed at two opposite sides of the substraterespectively, the engagement of the two through slots and the coverelement defining the second adhesive bonding area. An additional stepmay be formed inside each of the through slots and configured forincreasing the area of the substrate within the through slots thatcontacts the second adhesive. Two openings may be formed at two oppositesides of the cover element respectively, the engagement of the twothrough slots and the two openings defining the second adhesive bondingarea. The two through slots and the two openings may be aligned formingtwo through cavities respectively, the through cavities being configuredfor receiving the second adhesive and providing paths for air to escapewhen the second adhesive is applied.

Two undercuts may be formed at two opposite sides of the substraterespectively, the engagement of the two undercuts and the cover elementdefining the second adhesive bonding area. The undercuts may be alignedwith and extending from edges of the cover element, forming a cavityunderneath the cover element, the cavity being configured for receivingthe second adhesive so that the second adhesive is extended from thecavity to cover sides of the cover element.

Two cutouts may be formed at two opposite sides of the cover elementrespectively and aligned with the two undercuts respectively, theengagement of the two undercuts and the two cutouts defining the secondadhesive bonding area.

In another aspect, the present patent application provides a method formaking an optoelectronic package. The method includes: applying a firstadhesive to a first adhesive bonding area of a cover element; placingthe cover element onto a substrate so that the first adhesive bondingarea of the cover element is in direct contact with a predeterminedregion of the substrate; curing the first adhesive so as to secure thecover element onto the substrate; applying a second adhesive to a secondadhesive bonding area defined between the cover element and thesubstrate; and curing the second adhesive. The second adhesive bondingarea is defined through the engagement of the cover element and thesubstrate, and configured to allow the second adhesive to be in directcontact with both the cover element and the substrate, and confinedwithin a localized area.

The method may further include assembling semiconductor chips andoptoelectronic components onto the substrate before applying the firstadhesive to the first adhesive bonding area.

The method may further include employing a precision placement processto align functional features on the cover element with theoptoelectronic components.

The second adhesive may be cured by a longer curing process than thefirst adhesive. The first adhesive may be cured by ultra-violet light.The second adhesive may be cured by thermal curing.

In yet another aspect, the present patent application provides anoptoelectronic package that includes a substrate and a cover elementbonded onto the substrate. The cover element defines a cavity foraccommodating semiconductor chips and optoelectronic components, andincludes functional features aligned with the optoelectronic components.The cover element includes a first adhesive bonding area configured forreceiving a first adhesive and being bonded with a predetermined regionof the substrate by the first adhesive. The engagement of the coverelement and the substrate defines a second adhesive bonding area. Thesecond adhesive bonding area is configured for receiving a secondadhesive and confining the second adhesive within a localized area.

The cover element may include two steps defining two cutout regionsformed at two opposite sides of the cover element respectively, theengagement of the two steps and the substrate defining the secondadhesive bonding area.

Two through slots may be formed at two opposite sides of the substraterespectively, the engagement of the two through slots and the coverelement defining the second adhesive bonding area.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a conventional optoelectronicpackage with a precision-aligned functional cover element.

FIG. 2 is a flow chart illustrating a method for making anoptoelectronic package according to an embodiment of the present patentapplication.

FIG. 3 a is an exploded view of an optoelectronic package according toan embodiment of the present patent application.

FIG. 3 b is a bottom view of the optoelectronic package depicted in FIG.3 a.

FIG. 3 c is a perspective view of the optoelectronic package depicted inFIG. 3 a.

FIG. 3 d is a cross-sectional view of the optoelectronic packagedepicted in FIG. 3 a.

FIG. 4 a is an exploded view of an optoelectronic package according toanother embodiment of the present patent application.

FIG. 4 b is a perspective view of the optoelectronic package depicted inFIG. 4 a.

FIG. 4 c is a partial magnified view of the optoelectronic packagedepicted in FIG. 4 a illustrating a second adhesive bonding area.

FIG. 4 d is a cross-sectional view of the optoelectronic packagedepicted in FIG. 4 a.

FIG. 5 a is an exploded view of an optoelectronic package according toyet another embodiment of the present patent application.

FIG. 5 b is a bottom view of a cover of the optoelectronic packagedepicted in FIG. 5 a.

FIG. 5 c is a bottom perspective view of the optoelectronic packagedepicted in FIG. 5 a.

FIG. 5 d is a cross-sectional view of the optoelectronic packagedepicted in FIG. 5 a.

FIG. 6 a is an exploded view of an optoelectronic package according tostill another embodiment of the present patent application.

FIG. 6 b is a perspective view of the assembled optoelectronic packagedepicted in FIG. 6 a.

FIG. 6 c is a bottom perspective view of the optoelectronic packagedepicted in FIG. 6 a illustrating a second adhesive bonding area.

FIG. 6 d shows cross-sectional views of the optoelectronic packagedepicted in FIG. 6 a.

FIG. 7 a is an exploded view of an optoelectronic package according tostill another embodiment of the present patent application.

FIG. 7 b is a cross-sectional view of the optoelectronic packagedepicted in FIG. 7 a.

FIG. 8 a is an exploded view of an optoelectronic package according tostill another embodiment of the present patent application.

FIG. 8 b is a perspective view of the assembled optoelectronic packagedepicted in FIG. 8 a.

FIG. 8 c is a cross-sectional view of the optoelectronic packagedepicted in FIG. 8 a.

DETAILED DESCRIPTION

Reference will now be made in detail to a preferred embodiment of theoptoelectronic package and the method for making the same disclosed inthe present patent application, examples of which are also provided inthe following description. Exemplary embodiments of the optoelectronicpackage and the method for making the same disclosed in the presentpatent application are described in detail, although it will be apparentto those skilled in the relevant art that some features that are notparticularly important to an understanding of the optoelectronic packageand the method for making the same may not be shown for the sake ofclarity.

Furthermore, it should be understood that the optoelectronic package andthe method for making the same disclosed in the present patentapplication is not limited to the precise embodiments described belowand that various changes and modifications thereof may be effected byone skilled in the art without departing from the spirit or scope of theprotection. For example, elements and/or features of differentillustrative embodiments may be combined with each other and/orsubstituted for each other within the scope of this disclosure.

FIG. 2 is a flow chart illustrating a method for making anoptoelectronic package according to an embodiment of the present patentapplication. In this method, a cover element is attached and bonded ontoa substrate to form a completed module. Referring to FIG. 2,semiconductor chips and optoelectronic components are first assembledonto the substrate before the cover bonding process. Subsequently, instep 1, a first adhesive is applied onto a first adhesive bonding areaof the cover element. In step 2, the cover element is placed onto thesubstrate, covering the populated components. The first adhesive bondingarea of cover element is in direct contact with the substrate surface. Aprecision placement process is employed to align functional features onthe cover element with the optoelectronic components. In step 3, thefirst adhesive is hardened by a fast curing process. One example of suchprocess includes curing by ultra-violet (UV) light. This step bonds thecover element onto the substrate while fixing the alignment of the twoparts to facilitate later processes. In step 4, a second adhesive isapplied onto a second adhesive bonding area defined between the coverelement and the substrate. The second adhesive bonding area is formedthrough the engagement of specific mechanical features on the coverelement and the substrate, and configured to allow the second adhesiveto come in direct contact with both the cover element and the substratebody while still being confined within a localized area. In step 5, asecond and longer curing process is employed to cure the secondadhesive. One example of such process is thermal curing. Such curingprovides sufficient bonding strength to ensure long-term adhesion whilemaintaining the alignment of the two parts.

In the above embodiment, a method for making an optoelectronic packageis provided. The method includes applying a first adhesive to a firstadhesive bonding area of a cover element; placing the cover element ontoa substrate so that the first adhesive bonding area of the cover elementis in direct contact with a predetermined region of the substrate;curing the first adhesive so as to secure the cover element onto thesubstrate; applying a second adhesive to a second adhesive bonding areadefined between the cover element and the substrate; and curing thesecond adhesive. The second adhesive bonding area is defined through theengagement of the cover element and the substrate, and configured toallow the second adhesive to be in direct contact with both the coverelement and the substrate, and confined within a localized area.

FIG. 3 a is an exploded view of an optoelectronic package according toan embodiment of the present patent application. FIG. 3 b is a bottomview of the optoelectronic package depicted in FIG. 3 a. FIG. 3 c is aperspective view of the optoelectronic package depicted in FIG. 3 a.FIG. 3 d is a cross-sectional view of the optoelectronic packagedepicted in FIG. 3 a.

Referring to FIG. 3 a and FIG. 3 b, the optoelectronic package includesa substrate 12 and a cover element 11 bonded onto the substrate 12. Thecover element 11 defines a cavity 14 for accommodating semiconductorchips and optoelectronic components. Two steps 13 defining two cutoutregions are respectively formed at two opposite sides of the coverelement 11. The cover element 11 has a first adhesive application area15. There are no special design features on the substrate 12. As shownin FIG. 3 c, after the cover element 11 is bonded onto the substrate 12,the second adhesive is applied to a second adhesive bonding area 16, andflowing into a substrate region confined by the second adhesive bondingarea 16. The steps 13 in the second adhesive bonding area 16 increasethe adhesive contact area. The cured second adhesive forms the bondingregion 17, which holds the cover element 11 and the substrate 12together with high bonding force, as shown in FIG. 3 d.

In the above embodiment, an optoelectronic package is provided. Theoptoelectronic package includes: a substrate 12; a cover element 11bonded onto the substrate 12, the cover element 11 defining a cavity 14for accommodating semiconductor chips and optoelectronic components. Thecover element 11 includes a first adhesive bonding area 15 configuredfor receiving a first adhesive and being bonded with a predeterminedregion of the substrate 12 by the first adhesive. The engagement of thecover element 11 and the substrate 12 defines a second adhesive bondingarea 16. The second adhesive bonding area 16 is configured for receivinga second adhesive and confining the second adhesive within a localizedarea. In this embodiment, the cover element 11 includes two steps 13defining two cutout regions formed at two opposite sides of the coverelement 11 respectively, the engagement of the two steps 13 and thesubstrate 12 defining the second adhesive bonding area 16.

FIG. 4 a is an exploded view of an optoelectronic package according toanother embodiment of the present patent application. FIG. 4 b is aperspective view of the optoelectronic package depicted in FIG. 4 a.FIG. 4 c is a partial magnified view of the optoelectronic packagedepicted in FIG. 4 a illustrating a second adhesive bonding area. FIG. 4d is a cross-sectional view of the optoelectronic package depicted inFIG. 4 a. Referring to FIGS. 4 a-4 d, in this embodiment, the coverelement 21 has the same back side design as in the embodimentillustrated in FIG. 3 a. There are no special design features on thesubstrate 22. At the top side, there are two thinned-down regions 23formed at two opposite sides of the cover element 21. After bonding thecover element 21 onto 22, the second adhesive is applied to the regions23 and cured to form the bonding regions 25. Within each of the regions23, there is a through slot 24 configured for better confinement of thesecond adhesive.

In the above embodiment, the cover element 21 includes two thinned-downregions 23 formed at two opposite sides of the cover element 21respectively. The engagement of the two thinned-down regions 23 and thesubstrate 22 defines the second adhesive bonding area. A through hole 24is formed within each of the thinned-down regions 23 and configured forimproving the confinement of the second adhesive.

FIG. 5 a is an exploded view of an optoelectronic package according toyet another embodiment of the present patent application. FIG. 5 b is abottom view of a cover of the optoelectronic package depicted in FIG. 5a. FIG. 5 c is a bottom perspective view of the optoelectronic packagedepicted in FIG. 5 a. FIG. 5 d is a cross-sectional view of theoptoelectronic package depicted in FIG. 5 a. Referring to FIGS. 5 a-5 d,the area 34 is the region where the first adhesive is applied on thecover element 31. Through slots 33 are formed on the substrate 32. Whenthe cover element 31 is aligned and bonded with the substrate 32, theopenings of the through slots 33 are aligned with the region 37. Afterthe curing of the first adhesive, the second adhesive is applied fromthe back side of the assembly through the openings 35. The secondadhesive makes contact with the region 37 through the openings ofthrough slots 33 and forms the second adhesive bonding points 36. Anadditional step 38 is present inside the through slots 33 and configuredfor increasing the adhesive contact area.

In the above embodiment, two through slots 33 are formed at two oppositesides of the substrate 32 respectively. The engagement of the twothrough slots 33 and the cover element 31 defines the second adhesivebonding area. An additional step 38 is formed inside each of the throughslots 33 and configured for increasing the area of the substrate 32within the through slots 33 that contacts the second adhesive.

FIG. 6 a is an exploded view of an optoelectronic package according tostill another embodiment of the present patent application. FIG. 6 b isa perspective view of the assembled optoelectronic package depicted inFIG. 6 a. FIG. 6 c is a bottom perspective view of the optoelectronicpackage depicted in FIG. 6 a illustrating a second adhesive bondingarea. FIG. 6 d shows cross-sectional views of the optoelectronic packagedepicted in FIG. 6 a. Referring to FIGS. 6 a-6 d, openings 43 and 44 areformed on the cover element 41 and the substrate 42 respectively. Whenthe cover element 41 and the substrate 42 are aligned and bonded withthe first adhesive, the openings 43 and 44 are also aligned forming athrough cavity 47 in which the second adhesive is applied. The throughcavity 47 provides a path for air to escape when the second adhesive isapplied.

In the above embodiment, two openings 43 are formed at two oppositesides of the cover element 41 respectively. The engagement of the twothrough slots 44 and the two openings 43 defines the second adhesivebonding area. The two through slots 44 and the two openings 43 arealigned forming two through cavities 47 respectively. The throughcavities 47 are configured for receiving the second adhesive andproviding paths for air to escape when the second adhesive is applied.

FIG. 7 a is an exploded view of an optoelectronic package according tostill another embodiment of the present patent application. FIG. 7 b isa cross-sectional view of the optoelectronic package depicted in FIG. 7a. Referring to FIGS. 7 a-7 b, in this embodiment, undercuts 53 areformed on the substrate 52. When the cover element 51 is aligned withthe substrate 52 and bonded onto the substrate 52 with the firstadhesive, the undercuts 53 are aligned with and extending from the edgesof the cover element 51 forming a cavity 54 underneath the cover element51. The second adhesive is applied into the cavity 54 and extended tocover the sides of the cover element 51.

In the above embodiment, two undercuts 53 are formed at two oppositesides of the substrate 52 respectively, the engagement of the twoundercuts 53 and the cover element 51 defining the second adhesivebonding area. The undercuts 53 are aligned with and extending from edgesof the cover element 51, forming a cavity 54 underneath the coverelement. The cavity 54 is configured for receiving the second adhesiveso that the second adhesive is extended from the cavity 54 to coversides of the cover element 51.

FIG. 8 a is an exploded view of an optoelectronic package according tostill another embodiment of the present patent application. FIG. 8 b isa perspective view of the assembled optoelectronic package depicted inFIG. 8 a. FIG. 8 c is a cross-sectional view of the optoelectronicpackage depicted in FIG. 8 a. Referring to FIGS. 8 a-8 c, in thisembodiment, there are additional cutouts 57 formed at the sides of thecover element 56. The cutouts 57 are aligned with the undercut 53 afterthe first adhesive bonding. This allows the second adhesive to havelarger contact area with the cover element 56.

In the above embodiment, two cutouts 57 are formed at two opposite sidesof the cover element 56 respectively and aligned with the two undercuts53 respectively. The engagement of the two undercuts 53 and the twocutouts 57 defines the second adhesive bonding area.

In another embodiment, an optoelectronic package includes a substrateand a cover element bonded onto the substrate. The cover element definesa cavity for accommodating semiconductor chips and optoelectroniccomponents, and includes functional features aligned with theoptoelectronic components. The cover element includes a first adhesivebonding area configured for receiving a first adhesive and being bondedwith a predetermined region of the substrate by the first adhesive. Theengagement of the cover element and the substrate defines a secondadhesive bonding area. The second adhesive bonding area is configuredfor receiving a second adhesive and confining the second adhesive withina localized area.

The optoelectronic package provided by the above-mentioned embodimentsachieves benefits such as good bonding strength between the coverelement and the substrate over the entire product life, minimal shift ormovement of the cover element during the final curing, and minimal shiftor movement of the cover element in the lifetime of the product. Thesebenefits help to maintain the function of the assembly to be stable, toincrease the yield of the assembly, and to increase the integrity of thepackage to pass the mechanical reliability tests required in theindustry.

While the present patent application has been shown and described withparticular references to a number of embodiments thereof, it should benoted that various other changes or modifications may be made withoutdeparting from the scope of the present invention.

What is claimed is:
 1. A method for making an optoelectronic package,the method comprising: applying a first adhesive to a first adhesivebonding area of a cover element; placing the cover element onto asubstrate so that the first adhesive bonding area of the cover elementis in direct contact with a predetermined region of the substrate;curing the first adhesive so as to secure the cover element onto thesubstrate; applying a second adhesive to a second adhesive bonding areadefined between the cover element and the substrate; and curing thesecond adhesive; wherein: the second adhesive bonding area is definedthrough the engagement of the cover element and the substrate, andconfigured to allow the second adhesive to be in direct contact withboth the cover element and the substrate, and confined within alocalized area.
 2. The method of claim 1 further comprising assemblingsemiconductor chips and optoelectronic components onto the substratebefore applying the first adhesive to the first adhesive bonding area.3. The method of claim 1 further comprising employing a precisionplacement process to align functional features on the cover element withthe optoelectronic components.
 4. The method of claim 1, wherein thesecond adhesive is cured by a longer curing process than the firstadhesive.
 5. The method of claim 4, wherein the first adhesive is curedby ultra-violet light.
 6. The method of claim 4, wherein the secondadhesive is cured by thermal curing.
 7. The method of claim 1, whereintwo through slots are formed at two opposite sides of the substraterespectively, the engagement of the two through slots and the coverelement defining the second adhesive bonding area.
 8. The method ofclaim 7, wherein an additional step is formed inside each of the throughslots and configured for increasing the area of the substrate within thethrough slots that contacts the second adhesive.
 9. The method of claim7, wherein two openings are formed at two opposite sides of the coverelement respectively, the engagement of the two through slots and thetwo openings defining the second adhesive bonding area.
 10. The methodof claim 9, wherein the two through slots and the two openings arealigned forming two through cavities respectively, the through cavitiesbeing configured for receiving the second adhesive and providing pathsfor air to escape when the second adhesive is applied.